Freescale Semiconductor /MKW40Z4 /ZLL /IRQSTS

Sequence-end Interrupt Status bit. A ‘1’ indicates the completion of an autosequence. This interrupt will assert whenever the Sequence Manager transitions from non-idle to idle state, for any reason. This is write a ‘1’ to clear bit.

0 (0): A Sequencer Interrupt has not occurred

1 (1): A Sequencer Interrupt has occurred

Transmitter Interrupt Status bit. A ‘1’ indicates the completion of a transmit operation. This is write a ‘1’ to clear bit.

0 (0): A TX Interrupt has not occurred

1 (1): A TX Interrupt has occurred

Receiver Interrupt Status bit. A ‘1’ indicates the completion of a receive operation. This is write a ‘1’ to clear bit.

0 (0): A RX Interrupt has not occurred

1 (1): A RX Interrupt has occurred

Clear Channel Assessment Interrupt Status bit. A ‘1’ indicates completion of CCA operation. This is write ‘1’ to clear bit.

0 (0): A CCA Interrupt has not occurred

1 (1): A CCA Interrupt has occurred

Receiver Byte Count Water Mark Interrupt Status bit. A ‘1’ indicates that the number of bytes specified in the RX_WTR_MARK register has been reached. This is write a ‘1’ to clear bit.

0 (0): A RX Watermark Interrupt has not occurred

1 (1): A RX Watermark Interrupt has occurred

Receiver Packet Filter Fail Interrupt Status bit. A ‘1’ indicates that the most-recently received packet has been rejected due to elements within the packet. This is write a ‘1’ to clear bit. In Dual PAN mode, FILTERFAIL_IRQ applies to either or both networks, as follows: A: If PAN0 and PAN1 occupy different channels and CURRENT_NETWORK=0, FILTERFAIL_IRQ applies to PAN0. B: If PAN0 and PAN1 occupy different channels and CURRENT_NETWORK=1, FILTERFAIL_IRQ applies to PAN1. C: If PAN0 and PAN1 occupy the same channel, FILTERFAIL_IRQ is the logical ‘AND’ of the individual PANs’ Filter Fail status.

0 (0): A Filter Fail Interrupt has not occurred

1 (1): A Filter Fail Interrupt has occurred

PLL Un-lock Interrupt Status bit. A ‘1’ indicates an unlock event has occurred in the PLL. This is write a ‘1’ to clear bit.

0 (0): A PLL Unlock Interrupt has not occurred

1 (1): A PLL Unlock Interrupt has occurred

Status of the frame pending bit of the frame control field for the most-recently received packet. Read-only.

Packet Buffer Underrun Error IRQ

0 (0): A Packet Buffer Underrun Error Interrupt has not occurred

1 (1): A Packet Buffer Underrun Error Interrupt has occurred

Composite TMR Status

0 (0): no TMRxIRQ is asserted

1 (1): At least one of the TMRxIRQ is asserted (TMR1IRQ, TMR2IRQ, TMR3IRQ, or TMR4IRQ)

Poll Indication

0 (0): the received packet was not a data request

1 (1): the received packet was a data request, regardless of whether a Source Address table match occurred, or whether Source Address Management is enabled or not

Source Address Match Status

CCA Status

0 (0): IDLE

1 (1): BUSY

CRC Valid Status

0 (0): Rx FCS != calculated CRC (incorrect)

1 (1): Rx FCS = calculated CRC (correct)

Timer 1 IRQ

Timer 2 IRQ

Timer 3 IRQ

Timer 4 IRQ

Timer Comperator 1 Interrupt Mask bit

0 (0): allows interrupt when comparator matches event timer count

1 (1): Interrupt generation is disabled, but a TMR1IRQ flag can be set

Timer Comperator 2 Interrupt Mask bit

0 (0): allows interrupt when comparator matches event timer count

1 (1): Interrupt generation is disabled, but a TMR2IRQ flag can be set

Timer Comperator 3 Interrupt Mask bit

0 (0): allows interrupt when comparator matches event timer count

1 (1): Interrupt generation is disabled, but a TMR3IRQ flag can be set

Timer Comperator 4 Interrupt Mask bit

0 (0): allows interrupt when comparator matches event timer count

1 (1): Interrupt generation is disabled, but a TMR4IRQ flag can be set

Receive Frame Length